Features Configuration Bits RAM map SFR map

PIC10LF320
Bank 0

INDF | 0x000
TMR0 | 0x001
PCL | 0x002
STATUS | 0x003
FSR | 0x004
PORTA | 0x005
TRISA | 0x006
LATA | 0x007
ANSELA | 0x008
WPUA | 0x009
PCLATH | 0x00A
INTCON | 0x00B
PIR1 | 0x00C
PIE1 | 0x00D
OPTION_REG | 0x00E
PCON | 0x00F
OSCCON | 0x010
TMR2 | 0x011
PR2 | 0x012
T2CON | 0x013
PWM1DCL | 0x014
PWM1DCH | 0x015
PWM1CONPWM1CON0 | 0x016
PWM2DCL | 0x017
PWM2DCH | 0x018
PWM2CONPWM2CON0 | 0x019
IOCAP | 0x01A
IOCAN | 0x01B
IOCAF | 0x01C
FVRCON | 0x01D
ADRES | 0x01E
ADCON | 0x01F
PMADRPMADRL | 0x020
PMADRH | 0x021
PMDATPMDATL | 0x022
PMDATH | 0x023
PMCON1 | 0x024
PMCON2 | 0x025
CLKRCON | 0x026
NCO1ACCNCO1ACCL | 0x027
NCO1ACCH | 0x028
NCO1ACCU | 0x029
NCO1INCNCO1INCL | 0x02A
NCO1INCH | 0x02B
NCO1INCU | 0x02C
NCO1CON | 0x02D
NCO1CLK | 0x02E
WDTCON | 0x030
CLC1CON | 0x031
CLC1SEL0 | 0x032
CLC1SEL1 | 0x033
CLC1POL | 0x034
CLC1GLS0 | 0x035
CLC1GLS1 | 0x036
CLC1GLS2 | 0x037
CLC1GLS3 | 0x038
CWG1CON0 | 0x039
CWG1CON1 | 0x03A
CWG1CON2 | 0x03B
CWG1DBR | 0x03C
CWG1DBF | 0x03D
VREGCON | 0x03E
BORCON | 0x03F

SFR

SFR with alias name.

This page generated automatically by the device-help.pl program (2016-08-21 09:07:38 UTC) from the 8bit_device.info file (rev: 1.31) of mpasmx and from the gputils source package (rev: svn Unversioned directory). The mpasmx is included in the MPLAB X.