Features Configuration Bits RAM map SFR map

PIC18F458
Bank 15

RXF0SIDH | 0xF00
RXF0SIDL | 0xF01
RXF0EIDH | 0xF02
RXF0EIDL | 0xF03
RXF1SIDH | 0xF04
RXF1SIDL | 0xF05
RXF1EIDH | 0xF06
RXF1EIDL | 0xF07
RXF2SIDH | 0xF08
RXF2SIDL | 0xF09
RXF2EIDH | 0xF0A
RXF2EIDL | 0xF0B
RXF3SIDH | 0xF0C
RXF3SIDL | 0xF0D
RXF3EIDH | 0xF0E
RXF3EIDL | 0xF0F
RXF4SIDH | 0xF10
RXF4SIDL | 0xF11
RXF4EIDH | 0xF12
RXF4EIDL | 0xF13
RXF5SIDH | 0xF14
RXF5SIDL | 0xF15
RXF5EIDH | 0xF16
RXF5EIDL | 0xF17
RXM0SIDH | 0xF18
RXM0SIDL | 0xF19
RXM0EIDH | 0xF1A
RXM0EIDL | 0xF1B
RXM1SIDH | 0xF1C
RXM1SIDL | 0xF1D
RXM1EIDH | 0xF1E
RXM1EIDL | 0xF1F
TXB2CON | 0xF20
TXB2SIDH | 0xF21
TXB2SIDL | 0xF22
TXB2EIDH | 0xF23
TXB2EIDL | 0xF24
TXB2DLC | 0xF25
TXB2D0 | 0xF26
TXB2D1 | 0xF27
TXB2D2 | 0xF28
TXB2D3 | 0xF29
TXB2D4 | 0xF2A
TXB2D5 | 0xF2B
TXB2D6 | 0xF2C
TXB2D7 | 0xF2D
CANSTATRO4 | 0xF2E
TXB1CON | 0xF30
TXB1SIDH | 0xF31
TXB1SIDL | 0xF32
TXB1EIDH | 0xF33
TXB1EIDL | 0xF34
TXB1DLC | 0xF35
TXB1D0 | 0xF36
TXB1D1 | 0xF37
TXB1D2 | 0xF38
TXB1D3 | 0xF39
TXB1D4 | 0xF3A
TXB1D5 | 0xF3B
TXB1D6 | 0xF3C
TXB1D7 | 0xF3D
CANSTATRO3 | 0xF3E
TXB0CON | 0xF40
TXB0SIDH | 0xF41
TXB0SIDL | 0xF42
TXB0EIDH | 0xF43
TXB0EIDL | 0xF44
TXB0DLC | 0xF45
TXB0D0 | 0xF46
TXB0D1 | 0xF47
TXB0D2 | 0xF48
TXB0D3 | 0xF49
TXB0D4 | 0xF4A
TXB0D5 | 0xF4B
TXB0D6 | 0xF4C
TXB0D7 | 0xF4D
CANSTATRO2 | 0xF4E
RXB1CON | 0xF50
RXB1SIDH | 0xF51
RXB1SIDL | 0xF52
RXB1EIDH | 0xF53
RXB1EIDL | 0xF54
RXB1DLC | 0xF55
RXB1D0 | 0xF56
RXB1D1 | 0xF57
RXB1D2 | 0xF58
RXB1D3 | 0xF59
RXB1D4 | 0xF5A
RXB1D5 | 0xF5B
RXB1D6 | 0xF5C
RXB1D7 | 0xF5D
CANSTATRO1 | 0xF5E
RXB0CON | 0xF60
RXB0SIDH | 0xF61
RXB0SIDL | 0xF62
RXB0EIDH | 0xF63
RXB0EIDL | 0xF64
RXB0DLC | 0xF65
RXB0D0 | 0xF66
RXB0D1 | 0xF67
RXB0D2 | 0xF68
RXB0D3 | 0xF69
RXB0D4 | 0xF6A
RXB0D5 | 0xF6B
RXB0D6 | 0xF6C
RXB0D7 | 0xF6D
CANSTAT | 0xF6E
CANCON | 0xF6F
BRGCON1 | 0xF70
BRGCON2 | 0xF71
BRGCON3 | 0xF72
CIOCON | 0xF73
COMSTAT | 0xF74
RXERRCNT | 0xF75
TXERRCNT | 0xF76
PORTA | 0xF80
PORTB | 0xF81
PORTC | 0xF82
PORTD | 0xF83
PORTE | 0xF84
LATA | 0xF89
LATB | 0xF8A
LATC | 0xF8B
LATD | 0xF8C
LATE | 0xF8D
DDRATRISA | 0xF92
DDRBTRISB | 0xF93
DDRCTRISC | 0xF94
DDRDTRISD | 0xF95
DDRETRISE | 0xF96
PIE1 | 0xF9D
PIR1 | 0xF9E
IPR1 | 0xF9F
PIE2 | 0xFA0
PIR2 | 0xFA1
IPR2 | 0xFA2
PIE3 | 0xFA3
PIR3 | 0xFA4
IPR3 | 0xFA5
EECON1 | 0xFA6
EECON2 | 0xFA7
EEDATA | 0xFA8
EEADR | 0xFA9
RCSTA | 0xFAB
TXSTA | 0xFAC
TXREG | 0xFAD
RCREG | 0xFAE
SPBRG | 0xFAF
T3CON | 0xFB1
TMR3TMR3L | 0xFB2
TMR3H | 0xFB3
CMCON | 0xFB4
CVRCON | 0xFB5
ECCPAS | 0xFB6
ECCP1DEL | 0xFB7
ECCP1CON | 0xFBA
ECCPR1ECCPR1L | 0xFBB
ECCPR1H | 0xFBC
CCP1CON | 0xFBD
CCPR1CCPR1L | 0xFBE
CCPR1H | 0xFBF
ADCON1 | 0xFC1
ADCON0 | 0xFC2
ADRESADRESL | 0xFC3
ADRESH | 0xFC4
SSPCON2 | 0xFC5
SSPCON1 | 0xFC6
SSPSTAT | 0xFC7
SSPADD | 0xFC8
SSPBUF | 0xFC9
T2CON | 0xFCA
PR2 | 0xFCB
TMR2 | 0xFCC
T1CON | 0xFCD
TMR1TMR1L | 0xFCE
TMR1H | 0xFCF
RCON | 0xFD0
WDTCON | 0xFD1
LVDCON | 0xFD2
OSCCON | 0xFD3
T0CON | 0xFD5
TMR0TMR0L | 0xFD6
TMR0H | 0xFD7
STATUS | 0xFD8
FSR2L | 0xFD9
FSR2H | 0xFDA
PLUSW2 | 0xFDB
PREINC2 | 0xFDC
POSTDEC2 | 0xFDD
POSTINC2 | 0xFDE
INDF2 | 0xFDF
BSR | 0xFE0
FSR1L | 0xFE1
FSR1H | 0xFE2
PLUSW1 | 0xFE3
PREINC1 | 0xFE4
POSTDEC1 | 0xFE5
POSTINC1 | 0xFE6
INDF1 | 0xFE7
WREG | 0xFE8
FSR0L | 0xFE9
FSR0H | 0xFEA
PLUSW0 | 0xFEB
PREINC0 | 0xFEC
POSTDEC0 | 0xFED
POSTINC0 | 0xFEE
INDF0 | 0xFEF
INTCON3 | 0xFF0
INTCON2 | 0xFF1
INTCONINTCON1 | 0xFF2
PRODPRODL | 0xFF3
PRODH | 0xFF4
TABLAT | 0xFF5
TBLPTRTBLPTRL | 0xFF6
TBLPTRH | 0xFF7
TBLPTRU | 0xFF8
PCPCL | 0xFF9
PCLATH | 0xFFA
PCLATU | 0xFFB
STKPTR | 0xFFC
TOSTOSL | 0xFFD
TOSH | 0xFFE
TOSU | 0xFFF

SFR

SFR with alias name.

SFR on Access Area.

This page generated automatically by the device-help.pl program (2016-08-21 09:07:42 UTC) from the 8bit_device.info file (rev: 1.31) of mpasmx and from the gputils source package (rev: svn Unversioned directory). The mpasmx is included in the MPLAB X.